Pulse counters are known which have the capacity to handle input signals with pulses in the megahertz frequency range. Conventionally such high speed pulse counters depend on the selection of a gating time related to the frequency of pulses being counted; the gating time being the time interval during which pulses are totalised. In practice hitherto the gating time has been selected either manually on the basis of the operative knowing the probable range or automatically through the use of an overflow pulse.
The use of an overflow pulse leads to the designation of a high speed counter as an auto-ranging counter and the present invention is concerned with an improvement to such auto-ranging counters.
Another technique employed with high speed counters is to employ a divider circuit to mathematically divide the input signal to be counted. In other words, assuming a regular frequency for the input signal over the input or measuring interval, a decade division of the input signal is accomplished by passing the input signal to the counter via a divider circuit. Such a circuit is only employer at input signal frequencies such that for the gating times available to the counter, are practicable for the sub-divided frequency of the high speed pulses. Normally the divider circuit has decade steps and is manually actuated by the operator working down from the highest range of possible frequency ranges.